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SM5956A 6-channel Asynchronous Sample Rate Converter
OVERVIEW
The SM5956A is a digital audio signal, asynchronous sample rate converter LSI. It reads 6-channel 16/20/24bit word length input data, and 16/20/24-bit word length output data. It also features a built-in digital deemphasis filter, direct muting and digital audio interface output.
FEATURES
Functions
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PINOUT
(Top view)
OMOD0 OMOD1 OWL0 OWL1 BCKO LRCO DITO
26
I I I
I
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I
I I
I
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I
I
I I
L/R 6-channel processing (2-channel stereo, 3-system processing) Input sample rate range: 10kHz to 200kHz Output sample rate range: 30kHz to 50kHz Operating sample rate conversion ratio (fso/fsi)*1 * 0.45 to 4.41 (SCKSLN = L, 512fso operation) * 0.225 to 4.41 (SCKSLN = H, 768fso operation) *1 : fsi = input sample rate fso = output sample rate Asynchronous input timing and output timing clock inputs System clock input * Input system clock: 1fsi (LRCI) * Output-system clock: 512fso/768fso (input on SCK) Deemphasis filter function * IIR filter structure * 44.1kHz, 48kHz, 32kHz input sample rate fsi compatible Direct mute function Through mode * Input data passed directly to the outputs Digital audio interface output * DIA input data undergoes sample rate conversion and is output biphase mark encoded Output data clocks (LRCO, BCKO) * LRCO rate: 1fso * BCKO rate: 64fso (SCKSLN = L, 512fso operation) 48fso (SCKSLN = H, 768fso operation) * Slave mode: Data is output at a rate dictated by an externally input signal * Master mode: Sample rate is generated internally from the output-system clock, and supplied as an output MCU interface * 3-wire serial interface 5V tolerant inputs for direct connection to 5V devices 3.3V single supply Package: 48-pin QFP
DOC
DOA
DOB
36
35
34
33
32
31
30
29
28
27
25
VDD
VSS
VDD TEST0 TEST1 TEST2 TEST3 SCK VSS SCKSLN ERROR RSTN SELFN VSS
37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21 20 19 18 17 16 15 14 13
VSS OEDITON SLAVEN THROUN DMUTEN MLE MDT MCK FS1 FS0 DEEMN VDD
IMOD1 10
TEST4 11
PACKAGE DIMENSIONS
(Unit: mm)
9 0.4 7 0.1
+ 0.075 0.125 - 0.025
7 0.1
9 0.4
IMOD0
IWL0
BCKI
IWL1
LRCI
VDD
VSS 12
1
2
3
4
5
6
7
8
DIA
DIB
DIC
9
1.4 0.1
1.7 MAX
0 ~ 10
+ 0.09 0.18 - 0.05
Note. Dimensions without tolerance are reference values.
ORDERING INFORMATION
Device SM5956AF Package 48-pin QFP
0.1
0.5
0.08
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0.5 0.2
SM5956A
FEATURES
Interfaces
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Converter Performance
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Input data format * 2s-complement, MSB-first, L/R alternating serial IIS/non-IIS formats
Format IMOD1 L L H H IMOD0 L H L H
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IIS MSB-first left-justified MSB-first right-justified MSB-first right-justified
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Input word length * 16/20/24-bit
Input word length 16 bits 20 bits 24 bits 24 bits IWL1 L L H H IWL0 L H L H
Internal data word length: 20 bits Deemphasis filter characteristics (IIR filter) * Gain deviation from ideal filter characteristic: 0.03dB Anti-aliasing LPF characteristics * Passband ripple: 0.0001dB * Stopband attenuation: > 98dB Converter noise levels * Internal calculation noise: -96dB * Output round-off noise: 16-bit output mode : -98dB 20-bit output mode : -122dB 24-bit output mode : -146dB
Input word length Output word length 16 bits 16 bits 20 bits 24 bits -92.3dB -94.0dB -94.1dB 20 bits -94.0dB -96.0dB -96.1dB 24 bits -94.0dB -96.0dB -96.2dB
Combined theoretical S/N
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Output data format * 2s-complement, MSB-first, L/R alternating serial IIS/non-IIS format * Continuous bit clock (64fso/48fso)
Format OMOD1 L L H H OMOD0 L H L H
IIS MSB-first left-justified MSB-first right-justified MSB-first right-justified
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Output word length * 16/20/24-bit
Output word length 16 bits 20 bits 24 bits 24 bits OWL1 L L H H OWL0 L H L H
Structure
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Silicon-gate CMOS process
Applications
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Sample rate conversion between digital audio equipment (AV amplifiers, CD-R/RW, MD, DVC etc.) Sample rate conversion in commercial recording/editing equipment
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SM5956A
BLOCK DIAGRAM
LRCI
BCKI
DIA, DIB, DIC
ERROR SCK SCKSLN RSTN SELFN Sequencer block Input data interface
IMOD0 IMOD1 IWL0
Interpolation operation Arithmetic operation block Output data operation
IWL1
Interpolation filter operation
DEEMN
Conversion rate detector
Output timing operation
Deemphasis filter operation
FS0 FS1
MCK MDT MLE MCU interface
Output operation
OMOD0 DITO OEDITON OMOD1
Digital audio interface
Output data interface
OWL0 OWL1
THROUN SLAVEN DMUTEN
Through, mute, and slave mode control
LRCO BCKO
DOA, DOB, DOC
PIN DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Name VDD LRCI BCKI DIA DIB DIC IWL0 IWL1 IMOD0 IMOD1 TEST4 VSS VDD I/O1 - Is Is Is Is Is I I I I Id - - VDD supply (3.3V) Sample rate clock input (fsi) Bit clock input (32fsi to 64fsi) Data input A Data input B Data input C Input word length select 0 Input word length select 1 See "Input Interface Settings" Input format select 0 Input format select 1 Test input Ground (0V) VDD supply (3.3V) Test - - Normal - - Function HIGH - - - - - - LOW - - - - - -
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SM5956A
No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name DEEMN FS0 FS1 MCK MDT MLE DMUTEN THROUN SLAVEN OEDITON VSS VDD DITO OMOD1 OMOD0 OWL1 OWL0 DOC DOB DOA BCKO LRCO VSS VDD TEST0 TEST1 TEST2 TEST3 SCK VSS SCKSLN ERROR RSTN SELFN VSS I/O1 I I I Is Is Is Id Id Id Id - - O I I I I O O O I/O I/O - - Id Id Id Id I - Id O Id Id - Deemphasis select Deemphasis frequency select 0 See "Sample Rate Conversion" Deemphasis frequency select 1 MCU interface clock input MCU interface data input MCU interface latch enable input Direct mute select Through-mode select Slave-mode select DIT output enable select Ground (0V) VDD supply (3.3V) Digital audio interface output Output format select 1 Output format select 0 See "Output Interface Settings" Output word length select 1 Output word length select 0 Data output C Data output B Data output A Bit clock input/output (48fso/64fso) Sample rate clock input/output (fso) Ground (0V) VDD supply (3.3V) Test input Test input Test input Test input Output-system clock input (512fso/768fso) Ground (0V) Output-system clock select Input error detector output Reset input Reset mode select Ground (0V) - - - - - - - Test Test Test Test - - 768fso - - External - - - - - - - - Normal Normal Normal Normal - - 512fso - Reset Automatic - - - - Output SRC Master L - - - - - - Mute Through Slave Output - - - Function HIGH OFF LOW ON
1. I = input, O = output, Id = input with pull-down, Is = Schmitt input, - = supply
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SM5956A
ABSOLUTE MAXIMUM RATINGS
VSS = 0V, VDD pins = VDD
Parameter Supply voltage Input voltage Output voltage Storage temperature Power dissipation Symbol VDD VI VO TSTG PW Rating -0.3 to 4.6 -0.3 to 5.5 -0.3 to VDD + 0.3 -55 to 125 700 Unit V V V C mW
Note. Ratings also apply when power is turned ON/OFF.
RECOMMENDED OPERATING CONDITIONS
VSS = 0V, VDD pins = VDD
Rating Parameter Supply voltage Operating temperature Symbol min VDD TOPR 3.0 -40 typ 3.3 25 max 3.6 85 V C Unit
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SM5956A
ELECTRICAL CHARACTERISTICS
DC Characteristics
VSS = 0V, VDD = 3.0 to 3.6V, Ta = -40 to 85C
Rating Parameter Pin Symbol (*A) Current consumption VDD IDD VIH Input voltage (*1)(*2) (*3)(*5) VIL VOH VOL Input leakage current (*1)(*2) (*5) (*3) (*3) (*1)(*2) (*3)(*5) ILH ILL IIH IIL Pull-down resistance Input load capacity RPD CLDI (*B) Condition min - - 2.0 0 BCKO, LRCO only IOH = -2.0mA IOL = 2.0mA VIN = VDD VIN = 0V VIN = VDD VIN = 0V 0 2.4 0 -1.0 -1.0 12.5 -1.0 40 - typ 75 100 - - - - - - - 33.0 - 100 10 max 90 mA 125 5.5 0.7 0.4 VDD 0.4 1.0 1.0 90.0 1.0 240 - V V V V V A A A A k pF Unit
Output voltage
(*4)(*5)
Input current
(*A) All outputs no load, system clock frequency FSCK = 24.576MHz, input word clock frequency FLRCI = 48kHz, SCKSLN = L (512fso), supply voltage VDD = 3.3V (*B) All outputs no load, system clock frequency FSCK = 36.864MHz, input word clock frequency FLRCI = 48kHz, SCKSLN = H (768fso), supply voltage VDD = 3.3V Note. See "Pin Classification" below for description of pins.
Pin classification
Symbol (*1) (*2) (*3) (*4) (*5) Inputs Schmitt inputs Pull-down inputs Outputs Input/Outputs Type Names SCK, IMOD0, IMOD1, IWL0, IWL1, DEEMN, FS0, FS1, OMOD0, OMOD1, OWL0, OWL1 LRCI, BCKI, DIA, DIB, DIC, MCK, MDT, MLE TEST0, TEST1, TEST2, TEST3, TEST4, DMUTEN, THROUN, SLAVEN, OEDITON, RSTN, SELFN, SCKSLN DOA, DOB, DOC, DITO, ERROR BCKO, LRCO
Note. The input and input/output pins are all 5V tolerant. The maximum input voltage that can be applied to these pins are 5.5V, if supply voltage is within the recommended operating voltage. If the input voltage is between 5.5V and VDD which is smaller than the recommended operating voltage, the device doesn't breakdown itself, but it maybe generate reverse current from the input pins to the supply voltage (VDD). Although input/output pins in input mode can accept 5.5V as the maximum input voltage, the maximum output voltage in output mode is VDD level. It is forbidden to add more voltage than VDD to output mode bidirectional pins (external pull-up or other means).
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SM5956A
AC Characteristics
Output-system clock (SCK input)
Rating Parameter Symbol Condition min SCKSLN = L Clock pulse cycle time tCY SCKSLN = H SCKSLN = L HIGH-level clock pulsewidth tCWH SCKSLN = H SCKSLN = L LOW-level clock pulsewidth Clock pulse duty tCWL SCKSLN = H 39.0 26.0 15.6 10.4 15.6 10.4 40 typ - - - - - - - max 65.1 ns 43.4 39.1 ns 26.0 39.1 ns 26.0 60 % Unit
VIH
SCK
0.5VDD
VIL tCWH tCY tCWL
Reset input (RSTN input)
Rating Parameter RSTN pulsewidth Symbol tRST Condition min 4tCY typ - max - ns Unit
Note. tCY = output-system clock (SCK input) cycle time
VIH
RSTN
0.5VDD
VIL
tRST
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SM5956A Serial inputs (LRCI, BCKI, DI* inputs)
Rating Parameter LRCI cycle time BCKI pulse cycle time BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth DI* setup time DI* hold time Last BCKI rising edge LRCI edge LRCI edge first BCKI rising edge Symbol tLICY tBICY tBICWH tBICWL tDIS tDIH tBLI tLBI Condition min 5 78 30 30 30 30 30 30 typ - - - - - - - - max 100 3125 - - - - - - s ns ns ns ns ns ns ns Unit
VIH
LRCI
0.5VDD
tBLI
BCKI
tLBI
VIL VIH
0.5VDD
tBICWH tBICY
tBICWL
VIL
VIH
DI*
0.5VDD
tDIS
tDIH
VIL
Note. DI*: DIA, DIB, DIC pins
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SM5956A Serial outputs (SLAVEN = L: LRCO, BCKO inputs, DO* outputs)
Rating Parameter LRCO cycle time BCKO pulse cycle time Symbol tLOCY SCKSLN = L tBOCY SCKSLN = H SCKSLN = L BCKO HIGH-level pulsewidth tBOCWH SCKSLN = H SCKSLN = L BCKO LOW-level pulsewidth Last BCKO rising edge LRCO edge LRCO edge first BCKO rising edge DO* output delay tBOCWL tBLO tLBO tDODL CL = 15pF SCKSLN = H Condition min 20 312.5 416.6 93.7 125 93.7 125 30 30 - typ - - - - - - - - - - max 33.34 520.8 ns 694.4 - - - - - - 30 ns s Unit
ns
ns ns ns
VIH
LRCO
0.5VDD
tBLO
BCKO
tLBO
VIL VIH
0.5VDD
tBOCWH
tBOCWL
VIL
tBOCY
VOH
DO*
0.5VDD
tDODL
Note. DO*: DOA, DOB, DOC pins
VOL
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SM5956A Serial outputs (SLAVEN = H: LRCO, BCKO, DO* outputs)
Rating Parameter Symbol Condition min SCKSLN = L LRCO cycle time tLOCY SCKSLN = H SCKSLN = L LRCO HIGH-level pulsewidth tLOCWH SCKSLN = H SCKSLN = L LRCO LOW-level pulsewidth tLOCWL SCKSLN = H SCKSLN = L BCKO pulse cycle time tBOCY SCKSLN = H SCKSLN = L BCKO HIGH-level pulsewidth tBOCWH SCKSLN = H SCKSLN = L BCKO LOW-level pulsewidth BCKO output delay LRCO output delay DO* output delay tBOCWL tBODL tLODL tDODL SCKSLN = H CL = 15pF CL = 15pF CL = 15pF - - - - - - - - - - - - - - - typ 512 768 256 384 256 384 8 16 4 8 4 8 - - - max - - - - - - - - - - - - 30 30 30 tCY Unit
tCY
tCY
tCY
tCY
tCY ns ns ns
Note. tCY = output-system clock (SCK input) cycle time
VIH
SCK
0.5VDD
tBODL
LRCO
tBODL
tLODL
VIL
VOH
0.5VDD
VOL VOH
BCKO
0.5VDD
tBOCWH tBOCWL
VOL
tBOCY
VOH
DO*
0.5VDD
tDODL
Note. DO*: DOA, DOB, DOC pins
VOL
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SM5956A MCU interface (MCK, MDT, MLE inputs)
Rating Parameter MCK cycle time MCK HIGH-level pulsewidth MCK LOW-level pulsewidth MDT setup time MDT hold time MLE LOW-level pulsewidth MLE setup time MLE hold time Rise time Fall time Symbol tMCY tMCWH tMCWL tMDS tMDH tMLWL tMLS tMLH tr tf Condition min 60 + 4tCY 30 + 2tCY 30 + 2tCY 30 + tCY 30 + tCY 30 + 2tCY 30 + tCY 30 + tCY - - typ - - - - - - - - - - max - - - - - - - - 100 100 ns ns ns ns ns ns ns ns ns ns Unit
Note. tCY = output-system clock (SCK input) cycle time
VIH
MDT
0.5VDD
VIL
tMDS tMDH tMCY
VIH
MCK
0.5VDD
tMCWH tMCWL
VIL
tMLS
tMLH
VIH
MLE
0.5VDD
tMLWL tf
MCK MDT MLE
VIL
tr
VIH
0.8VDD 0.2VDD
0.5VDD
VIL
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SM5956A
FUNCTIONAL DESCRIPTION
Input Interface Setting (IMOD0, IMOD1, IWL0, IWL1 pins)
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Input data format * 2s-complement, MSB-first, L/R alternating serial IIS/non-IIS format
Format IIS MSB-first left-justified MSB-first right-justified MSB-first right-justified IMOD1 L L H H IMOD0 L H L H
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Input word length * 16/20/24-bit
Input word length 16 bits 20 bits 24 bits 24 bits IWL1 L L H H IWL0 L H L H
Input timing See the timing for each of the input formats in figures 1 to 9.
Output Interface Settings (OMOD0, OMOD1, OWL0, OWL1, THROUN, SLAVEN pins)
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Output data format * 2s-complement, MSB-first, L/R alternating serial IIS/non-IIS format * Continuous bit clock (64fso/48fso)
Format IIS MSB-first left-justified MSB-first right-justified MSB-first right-justified OMOD1 L L H H OMOD0 L H L H
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Output word length * 16/20/24-bit
Output word length 16 bits 20 bits 24 bits 24 bits OWL1 L L H H OWL0 L H L H
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SM5956A Output mode select
Pins THROUN SLAVEN H H L Slave Mode Master Function Description LRCO, BCKO are derived by frequency division of the SCK input clock. LRCO, BCKO are supplied externally. When SCKSLN = L, BCKO is set to 64fso. When SCKSLN = H, BCKO is set to 48fso. The LRCI, BCKI, DIA, DIB, DIC inputs are fed directly to the LRCO, BCKO, DO* outputs. The DITO output is LOW-level. LRCO, BCKO pin state Outputs
Inputs
L
L or H
Through
Outputs
Output timing See the timing for each of the output formats in figures 10 to 18. In slave mode, note that the LRCO and BCKO as timing shown in figures 10 to 14 must be inputted externally. In through mode, note that the LRCI, BCKI, DI* inputs are passed to the outputs as-is, regardless of the output data format setting, and that DITO is a LOW-level output.
Note. DI*: DIA, DIB, DIC pins DO*: DOA, DOB, DOC pins
Output-System Clock (SCK, SCKSLN pins)
The output-system clock input must have a frequency of either 512fso or 768fso, where fso is the output-system sampling frequency. In master mode, the LRCO and BCKO signals are derived from this clock input by frequency division. This clock is also used as the system clock by the internal processing circuits.
SCKSLN L SCK input 512fso (fso = output-system sampling frequency) LRCO rate 1fso BCKO rate 64fso 768fso (fso = output-system sampling frequency) LRCO rate 1fso BCKO rate 48fso
H
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SM5956A
System Reset (ERROR, RSTN pins)
Under the following conditions, the system must be reset for normal conversion operation. Reset occurs using a LOW-level pulse input on the RSTN pin.
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When power is applied The reset should be released (RSTN = L H) after the supply voltage and LRCI, BCKI, SCK (and LRCO, BCKO in slave mode) clocks have stabilized. When the SCK clock is not continuous A reset is required when the SCK clock is dynamically switched or is not continuous, such as when switching the sampling frequency or when the clock momentarily stops due to the state of another IC. The reset should be released (RSTN = L H) after the SCK clock has stabilized. When the LRCI, BCKI inputs are not continuous (SELFN = H) A reset is required when the LRCI and BCKI clocks are dynamically switched or are not continuous, such as when switching the sampling frequency or when the clock momentarily stops due to the state of another IC. The ERROR pin goes L H to indicate the presence of an input problem, but the LSI continues to operate. The output generated as a result of the non-continuous clocks is not guaranteed, and it is recommended that the outputs be muted externally using DMUTEN or other means. The reset should be released (RSTN = L H) after the LRCI and BCKI clocks have stabilized. When the LRCO, BCKO inputs (in slave mode) are not continuous (SELFN = H) A reset is required when the LRCO and BCKO clocks are dynamically switched or are not continuous, such as when switching the sampling frequency or when the clock momentarily stops due to the state of another IC. The ERROR pin goes L H to indicate the presence of a slave input problem, but the LSI continues to operate. The output generated as a result of the non-continuous clocks is not guaranteed, and it is recommended that the outputs be muted externally using DMUTEN or other means. The reset should be released (RSTN = L H) after the LRCO and BCKO clocks have stabilized. A reset is required, in such cases where the error is generated, when the input/output sample rate conversion ratio is set to an incorrect value based on the non-continuous clock, resulting in incorrect output data. Output state during the reset interval The DOA, DOB, DOC, and DITO are tied LOW (See "Direct Mute" for operation after reset is released). In master mode, the LRCO and BCKO pins are also tied LOW. The required time to detect ERROR The ERROR detection block counts input-clock and output-clock for a given times (SLAVEN = L). ERROR pin changes HIGH-level when the observed counts does not agree with the expected counts. Therefore it needs some time for ERROR to reflect a condition of the clock (see table below). In the case of SELFN = L, the same time is required to change H L.
The ERROR by LRCI, BCKI stopping Output frequency [kHz] min [ms] 32 44.1 48 6.0 4.3 4.0 max [ms] 8.0 5.8 5.3 min [s] 93.8 68.0 62.5 max [s] 125.0 90.7 83.3 The ERROR by LRCO, BCKO stopping
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SM5956A
Reset Mode (SELFN pin)
The operation after a non-continuous LRCI/BCKI input clock or LRCO/BCKO input clock (in slave mode) is detected, as described in "System Reset" above, is selected by the SELFN pin.
SELFN L Function Automatic self reset when non-continuous input/output clocks are detected. The outputs are directly muted from the time when the non-continuous state is detected until the self reset is released. The ERROR output goes L H when non-continuous input/output clocks are detected. The output continues as-is during the time an external reset input is applied and released. Accordingly, to prevent incorrect output it is recommended that the outputs be directly muted using DMUTEN or other means.
H
Direct Mute (DMUTEN pin)
Direct mute ON/OFF
DMUTEN L H 0 data is output from the next output word. Audio data is output from the next output word. Function
Other mute operations Direct mute is also applied during reset input cycles.
RSTN L H 0 data is output from the next output word. Processor data is output after the 8th output word after RSTN goes HIGH. Function
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SM5956A
MCU Interface (MDT, MCK, MLE pins)
The SM5956A has a 3-wire serial MCU interface that is used to set the digital audio interface channel status data. Command format The commands from a microcontroller are input using the data input (MDT), bit clock (MCK), and load signal (MLE) inputs in bit serial format.
Address 4bit Data 12bit
MDT MCK MLE
A3 A2 A1 A0 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Write command format Register table
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Address: 0/H
Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Flag name Not used Not used Not used Not used Not used DMUTEN THROUN SLAVEN OEDITON DEEMN FS1 Set to 0 for normal operation Set to 0 for normal operation Set to 0 for normal operation Set to 0 for normal operation Set to 0 for normal operation Direct mute flag Through mode flag Slave mode flag DIT output enable flag Deemphasis select flag Deemphasis frequency select flag 1 Description Default 0 0 0 0 0 1 1 1 1 1 0
D0 FS0 Deemphasis frequency select flag 0 0 Note. Each flag operates using logic-OR with its corresponding external input pin of the same name. If only the MCU interface is used for control, all the pins corresponding to the flags must be set to their inactive level. When the flags are set to their default level, control using external pins is enabled.
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Address: 1/H
Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Flag name CNTL0 CNTL1 CNTL2 CNTL3 CATGY0 CATGY1 Not used LBIT CFS1 CFS2 CP1 Channel status bit 15 Channel status bit 24 Channel status bit 25 Channel status bit 28 Channel status bit 0 Channel status bit 1 Channel status bit 2. COPY flag Channel status bit 3. EMP flag Category code set flag 0 Category code set flag 1 (CATGY1, CATGY0) = category (0, 0) = "100 0000L" (CD) (0, 1) = "100 1100L" (DVD) (1, 0) = "100 0100L" (VCD) (1, 1) = "010 1100L" (SRC) Description Default 0 0 0 0 0 0 0 0 0 0 0 0
D0 CP2 Channel status bit 29 Note. This LSI can accept 4 type category codes shown in the table.
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SM5956A
Digital Audio Interface
When the OEDITON pin is LOW, the digital audio interface output on DITO pin is enabled. The input signal on DIA is sample rate converted, then a preamble is added and biphase mark encoded to form the output. In through mode, the DITO pin is forcibly tied LOW-level. When the SM5956A is operating in slave mode, the digital interface does not operate whenever the LRCO/BCKO are not operating as inputs.
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Sub Frame Frame 191
Sub Frame Frame 1
Frame 0
Start Block
Frame Format
0 34 LSB 78 27 MSB 28 31
(Sync Group)
Auxiliary
LSB
Preamble
Audio Sample Word
V
U
C
P
Validity Flag User Data Channel Status Parity Bit
Subframe Format Preamble The preamble is a specific pattern used for subframe and block synchronization and discrimination. It is assigned to the first four time slots (0 to 3) and is represented by 8 consecutive states when biphase mark encoded at the transfer rate. There are 3 preamble patterns. The leading subframe within a block has a B pattern preamble. All other channel 1 subframes have an M pattern preamble, and all channel 2 subframes have a W pattern preamble.
Channel coding Preamble Leading symbol: 0 B M W 11101000 11100010 11100100 Leading symbol: 1 00010111 00011101 00011011
Note. This LSI starts with a 0, therefore only the preamble for a 0 leading symbol is used.
Audio sample word and auxiliary data The audio sample word is represented by 20 bits in the digitized audio signal. The auxiliary data has various uses, including ancillary information or audio sample word length extension. The SM5956A audio data, however, is structured in 16-bit words, so bits 4 to 11 are output as 0 data. The audio data is output in bit positions 12 to 27 with the LSB first.
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SM5956A Validity flag The validity flag is set to 0 when the audio sample word transferred is valid, and is set to 1 when the data is invalid. The SM5956A sets the validity flag to 1 when direct mute is turned ON. User data The user data are user-defined bits originally provided in the standard in response to user requests, but the SM5956A sets all user data bits to 0.
0 0 12 24 36 : 1164 0 0 0 0 : 0 1 0 0 0 0 : 0 2 0 0 0 0 : 0 3 0 0 0 0 : 0 4 0 0 0 0 : 0 5 0 0 0 0 : 0 6 0 0 0 0 : 0 7 0 0 0 0 : 0 8 0 0 0 0 : 0 9 0 0 0 0 : 0 10 0 0 0 0 : 0 11 0 0 0 0 : 0
Channel status The channel status bits can be used to transfer various information, including audio sample word length, preemphasis, sampling frequency, time codes, source numbers, and destination codes. The SM5956A sets only 9 bits: CP1, CP2, LBIT, CNTL0 to 3, CFS1, and CFS2. The 15th bit of the 8th to 15th bit in the category code can be used to set LBIT status bit but 8th to 14th bit were determined by the category codes CATGY0, 1 (See "Register table"). All other bits are set to 0.
0 0 16 32 48 64 80 96 112 128 144 160 176 1 2 3 4 0 L=1 0 0 0 0 0 0 0 0 0 0 5 0 R=1 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 8 x CFS1 0 0 0 0 0 0 0 0 0 0 9 x CFS2 0 0 0 0 0 0 0 0 0 0 10 x 0 0 0 0 0 0 0 0 0 0 0 11 x 0 0 0 0 0 0 0 0 0 0 0 12 x CP1 0 0 0 0 0 0 0 0 0 0 13 0 CP2 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 15 LBIT 0 0 0 0 0 0 0 0 0 0 0
CNTL0 CNTL1 CNTL2 CNTL3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Parity bit The parity bit is used to indicate when an odd number of errors occur due to interface problems. The SM5956A sets the parity bit to 1 if the number of 1 bits in the other 27 data bits of the digital audio interface (excluding the preamble) is odd, and sets the parity bit to 0 if the number of 1 bits is even, thereby insuring that the number of 1 bits in the 28-bit data is always even.
SEIKO NPC CORPORATION --18
SM5956A
Sample Rate Conversion
The input-to-output sample rate conversion ratio can be arbitrarily set to any value between 0.45 to 4.41 (SCKSLN = L, 512fso operation) or 0.225 to 4.41 (SCKSLN = H, 768fso operation). The input-system sample rate (fsi) range is 10kHz to 200kHz, and the output-system sample rate (fso) range is 30kHz to 50kHz. However, note that due to system clock frequency limitations, fsi = 44.1kHz to fso = 192kHz conversion for example is not supported. Converter performance Internal data word length: 20 bits Deemphasis filter gain deviation from ideal characteristic: 0.03dB Anti-aliasing filter characteristic: Passband ripple 0.0001dB Stopband attenuation > 98dB Conversion noise levels I Internal quantization noise: -96dB I Output rounding-off noise: 16-bit output 20-bit output 24-bit output
Combined output theoretical S/N
Input word length Output word length 16 bits 16 bits 20 bits 24 bits -92.3dB -94.0dB -94.1dB 20 bits -94.0dB -96.0dB -96.1dB 24 bits -94.0dB -96.0dB -96.2dB
-98dB -122dB -146dB
Anti-aliasing filter characteristics
0 Attenuation [dB] -20 -40 -60 -80 -100 -120 0 0.1 0.2 0.3 Frequency [x fsi] 0.4 0.5 0.6
Anti-aliasing filter frequency response
SEIKO NPC CORPORATION --19
SM5956A
Deemphasis (DEEMN pin)
Traditional deemphasis filters employ an analog circuit construction. This device uses an IIR digital filter that faithfully reproduces the gain and phase response of analog filters. The filter coefficients are selected to match the input sample rate fsi (44.1kHz, 48.0kHz, 32.0kHz), set by the FS0 and FS1 pins. Deemphasis ON/OFF DEEMN = L : Deemphasis ON DEEMN = H: Deemphasis OFF Deemphasis filter coefficient selection The deemphasis filter coefficients are selected by the FS0 and FS1 pins.
fsi 44.1kHz 44.1kHz 48.0kHz 32.0kHz FS0 L H L H FS1 L L H H
Deemphasis filter characteristics
0.0 -2.0 Attenuation [dB] -4.0 -6.0 -8.0 -10.0 -12.0 10
44.1kHz 48kHz 32kHz
100
1000 Frequency [Hz]
10000
100000
Deemphasis filter frequency response
0 Phase characteristics [degree] -10 -20 -30 -40 -50 -60 -70 -80 -90 10 100 1000 Frequency [Hz] 10000 100000
32kHz 44.1kHz 48kHz
Deemphasis filter phase response
SEIKO NPC CORPORATION --20
SM5956A
Group Propagation Delay
tINPUT : Serial input data (fsi rate) read end timing (LRCI clock rising edge) tOUTPUT : Serial output data (fso rate) output start timing (LRCO clock rising edge) Cratio : Sample rate conversion ratio (fsi/fso) tOUTPUT - tINPUT = ((51.791 x Cratio + 41.557) 36)/fso (at SCKSLN = H, 768fso operation) tOUTPUT - tINPUT = ((51.122 x Cratio + 38.647) 36)/fso (at SCKSLN = L, 512fso operation)
1/fsi
Serial data input t INPUT
1/fso
t OUTPUT - t INPUT
Serial data output t OUTPUT
Data waveform image
t INPUT
t OUTPUT - t INPUT
t OUTPUT
Response Time
A certain amount of time is required to calculate the sample rate conversion ratio in the conversion rate detector. Assuming as a prerequisite that the SM5956A is supplied with a stable input-system sampling frequency (fsi: input on LRCI) and a stable output-system sampling frequency (fso: derived from the SCK clock), the time required after system reset to determine the sample rate conversion ratio with 16-bit precision is defined as the minimum response time, given by: Response time = 28140/fso (638ms at fso = 44.1kHz)
Input frequency fsi [kHz] 32 32 44.1 44.1 48 48 32 44.1 48 Output frequency fso [kHz] 44.1 48 32 48 32 44.1 32 44.1 48 Response time [ms] SCKSLN = L 594 557 822 473 799 478 447 325 298 SCKSLN = H 285 263 406 228 403 302 395 287 264
SEIKO NPC CORPORATION --21
SM5956A
TIMING DIAGRAMS
Input Timing (LRCI, BCKI, DIA, DIB, DIC pins)
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
15 16
12
15 16
Figure 1. 16-bit MSB-first right-justified (IMOD1 = H, IMOD0 = H, IWL1 = L, IWL0 = L) BCKI = 32fsi to 64fsi
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
19 20
12
19 20
Figure 2. 20-bit MSB-first right-justified (IMOD1 = H, IMOD0 = H, IWL0 = L, IWL0 = H) BCKI = 40fsi to 64fsi
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
23 24
12
23 24
Figure 3. 24-bit MSB-first right-justified (IMOD1 = H, IMOD0 = H, IWL1 = H, IWL0 = H) BCKI = 48fsi to 64fsi
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
15 16
12
15 16
Figure 4. 16-bit MSB-first left-justified (IMOD1 = L, IMOD0 = H, IWL1 = L, IWL0 = L) BCKI = 32fsi to 64fsi
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
19 20
12
19 20
Figure 5. 20-bit MSB-first left-justified (IMOD1 = L, IMOD0 = H, IWL1 = L, IWL0 = H) BCKI = 40fsi to 64fsi
SEIKO NPC CORPORATION --22
SM5956A
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
23 24
12
23 24
Figure 6. 24-bit MSB-first left-justified (IMOD1 = L, IMOD0 = H, IWL1 = H, IWL0 = H) BCKI = 48fsi to 64fsi
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
15 16
12
15 16
Figure 7. 16-bit IIS (IMOD1 = L, IMOD0 = L, IWL1 = L, IWL0 = L) BCKI = 64fsi only
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
19 20
12
19 20
Figure 8. 20-bit IIS (IMOD1 = L, IMOD0 = L, IWL1 = L, IWL0 = H) BCKI = 64fsi only
LRCI (fsi) BCKI (64fsi)
Lch
Rch
DIA, DIB, DIC
12
23 24
12
23 24
Figure 9. 24-bit IIS (IMOD1 = L, IMOD0 = L, IWL1 = H, IWL0 = H) BCKI = 64fsi only
SEIKO NPC CORPORATION --23
SM5956A
Output Timing (LRCO, BCKO, DOA, DOB, DOC pins)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
Lch
Rch
12
15 16
12
15 16
Figure 10. 16-bit MSB-first right-justified (OMOD1 = H, OMOD0 = H, OWL1 = L, OWL0 = L) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
19 20
12
19 20
Figure 11. 20-bit MSB-first right-justified (OMOD1 = H, OMOD0 = H, OWL1 = L, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
23 24
12
23 24
Figure 12. 24-bit MSB-first right-justified (OMOD1 = H, OMOD0 = H, OWL1 = H, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
15 16
12
15 16
Figure 13. 16-bit MSB-first left-justified (OMOD1 = L, OMOD0 = H, OWL1 = L, OWL0 = L) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
19 20
12
19 20
Figure 14. 20-bit MSB-first left-justified (OMOD1 = L, OMOD0 = H, OWL1 = L, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
SEIKO NPC CORPORATION --24
SM5956A
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
23 24
12
23 24
Figure 15. 24-bit MSB-first left-justified (OMOD1 = L, OMOD0 = H, OWL1 = H, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
15 16
12
15 16
Figure 16. 16-bit IIS (OMOD1 = L, OMOD0 = L, OWL1 = L, OWL0 = L) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
19 20
12
19 20
Figure 17. 20-bit IIS (OMOD1 = L, OMOD0 = L OWL1 = L, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
LRCO (fso) BCKO (64fso) DOA, DOB, DOC
12
Lch
Rch
23 24
12
23 24
Figure 18. 24-bit IIS (OMOD1 = L, OMOD0 = L, OWL1 = H, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above)
SEIKO NPC CORPORATION --25
SM5956A
TYPICAL APPLICATION CIRCUITS
Input Interface Connection Example
Connection with digital audio interface receiver (DIR: CS8414)
FSYNC SCK
SDATA Cc/F0 5V
LRCI BCKI DIA
DEEMN IMOD0 5V
DIR CS8414
SEL CS12/FCK M3 M2 M1
SM5956AF
IMOD1 TEST0 TEST1 TEST2
IWL0 IWL1 FS0 FS1
TEST3 TEST4
C
U
CBL
M0
MCU
Output Interface Connection Example
Connection with a MOST interface transceiver (OS8104)
24.576MHz (512fso)
SCK
LRCO BCKO
DOA
FSY SCK-SRC FL SR0-D3 5V /RD /WR PAR CP
RMCK
5V
SM5956AF
OMOD0 OMOD1 THROUN TEST0 TEST1 TEST2 TEST3 TEST4 SLAVEN OWL0 OWL1 SCKSLN
MOST OS8104
PAR SRC ASYNC PAD0 PAD1
SEIKO NPC CORPORATION --26
SM5956A
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter "Products") are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter "NPC"). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0412BE 2006.04
SEIKO NPC CORPORATION --27

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